PIC18F4539-E/PT【PDF 37/322 页】IC PIC MCU FLASH 12KX16 44TQFP

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2002 Microchip Technology Inc.

Preliminary

DS30485A-page 129

PIC18FXX39

16.3.3

ENABLING SPI I/O

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers, and then set the SSPEN bit. This

configures the SDI, SDO, SCK, and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed. That is:

SDI is automatically controlled by the SPI module

SDO must have TRISC<5> bit cleared

SCK (Master mode) must have TRISC<3> bit

cleared

SCK (Slave mode) must have TRISC<3> bit set

SS must have TRISC<4> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

16.3.4

TYPICAL CONNECTION

Figure 16-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite

edge of the clock. Both processors should be pro-

grammed to the same Clock Polarity (CKP), then both

controllers would send and receive data at the same

time. Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

Master sends data — Slave sends dummy data

Master sends data — Slave sends data

Master sends dummy data — Slave sends data

FIGURE 16-2:

SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

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